PCI, SCSI, and Fibre Channel

The PCI standard had its origins in the PC world, and has supplanted the two earlier standard microprocessor backplane buses�VME and Multibus. VME is, however, still used in real-time systems and in some process control applications. It started as a 16-bit bus and later grew to 32 bits; for the most part, VME-based systems used Motorola 68000-family microprocessors.

Multibus I was also a 16-bit bus initially, but Multibus systems tended to house Intel processors. While Intel extended the definition of Multibus I to 32 bits as Multibus II, the new version never saw wide adoption and disappeared fairly quickly.

We can summarize PCI�s major characteristics as follows:

� Two data transfer widths�32 bits and 64-bits

� Two clock rates�33MHz and 66MHz

� Various available bandwidths (133, 266, and 532 MB/sec), depending on clock rate and data width, and with burst-mode transfers

� The ability to support both 32 and 64 controllers on the same bus

� The ability to automatically discover the configuration of devices on the bus at system initialization (known as Plug and Play; this avoids tedious parameter setting in control tables)

� The ability to plug in and remove controllers without stopping the system, a capability known as hot plug.

PCI offers�even in its slowest version�substantially higher throughput than the earlier buses (and higher than MCA and EISA, too, which offered 33MB/sec and 40MB/sec respectively).

The significantly greater demands of more recent technologies, such as Gigabit Ethernet or Fibre Channel, have led to a proposal for a first extension to PCI, called PCI-X, with 32- or 64-bit data widths running at 66, 100 or 133MHz. The bandwidth of a 64-bit, 133MHz PCI-X interface is 1064MB/sec. Along with the physical enhancements, the bus protocol has also been improved in order to enhance efficiency.

The capabilities have been further extended into PCI-X 2.0, whose specifications were approved early in 2002. The goals of PCI-X 2.0 may be summarized as:

� Meet performance needs with an interface capable of handling 64-bit data widths running at 266 or 533MHz and with a throughput of 2128 or 4256 MB/sec respectively

� Support the use of earlier-generation cards to protect earlier investments (of course, this simply means that old cards must work with the new bus; a PCI-X 2.0 system with a mix of cards meeting earlier specifications and cards meeting 2.0 specifications will run at the speed of the slowest card)

� Become an industry standard

� Integrate well with the InfiniBand initiative (see below)

These various buses all represent the classical way to connect up peripherals and controllers �New I/O Structures: InfiniBand�we will examine the limitations of the classical approach and show why a new I/O architectural approach is called for.

Source of Information : Elsevier Server Architectures 2005